A 12-bit 50M samples/s digitally self-calibrated pipelined ADC
نویسندگان
چکیده
This thesis describes the different aspects of the design and implementation of a I2-bit 50M samplesjs pipelined non-binary radix 1.9 analog-to-digital converter. The converter architecture is made up of 14 stages with an interstage gain of 1.9 (non-binary radix). Each stage is made of one fully differential sample-and-hold amplifier (SHA), a I-bit sub-ADC (basically one comparator) and a I-bit DAC. The sub-DAC functionality is rolled in as part of the SHA switch capacitor architecture which is referred to as the multiplying DAC (MDAC). The self-calibration function is performed in a cyclical fashion and the entire pipeline is used to perform the calibration for each stage. The settling time on the MDAC is about 9ns with a gain of approximately SIdB. The entire pipeline has been implemented in a digital O.35/lm CMOS process.
منابع مشابه
A 12-bit 20-MS/s Pipelined ADC with Nested Digital Background Calibration*
A 12-b 20-MS/s pipelined ADC is calibrated using an algorithmic ADC, which is itself calibrated. With background calibration, the peak SNDR and SFDR of the pipeline are 70.8 dB and 93.3 dB, respectively. The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm in 0.35 m CMOS.
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